Features

• Packet or Cell BER Testing
• DC to 200 Mbits/s Data Rate, NRZ-1
• 256 Kbits Programmable WORD, PRBS, 1's Density and Selectable Mixed Mode
• Auto Search and Auto Sync Capability
• Controllable Gapped Tx Clock
• Automatic Eye-width Measurement and Extrapolation
• Clock/Data Delay up to 32 ns in 20 ps Increments
• Variable Data/Clock Amplitude and Offset Including ECL, PECL and High-Z TTL
• Mixed-mode Testing
• Pattern Editor Software for Custom Word Patterns (PC Windows-based)

Applications

• Wireless and Satellite Communications
• B-ISDN, Ethernet, TDMA and CDMA System Design
• Modem Development
• MPEG Frame Generation
• UTP, Fiber Optic Module Development
• Video-on-demand System Development

packetBERT PB200 Packet Generator and Error Detector

The PB200 is particularly suited to packet-based systems. It's ideal for component or sub-system development testing of TDMA, B-ISDN, FITL, ATM, Satellite modems and similar communications protocols.

The ability to generate a "Mixed Mode" data pattern allows flexibility in constructing many forms of test signals. Two separate programmable word memories of 16 to 256 Kbits in length allow the construction of a packet or cell that can consist of user-definable preamble, overhead and data. The PB200 data generator has one word memory that is used to define the overhead and preamble and a second word memory to define the data. Each memory can consist of a user-defined pattern or PRBS. The PB200 can also function as a fully featured non-packetized BERT.

Signal Analysis

For complete flexibility in signal analysis, the PB200 allows BER analysis on all, or only part, of the received digital information. Analysis can be performed on only the overhead, only the data or both overhead and data at the user's selection.

Unique packetBERT PB200 Features

The PB200 provides several unique features and capabilities that are not found on other BERT products in this class. The receiver has a clock/data deskew range of 32 ns and the ability to measure propagation delay. Along with the Auto Search setup capability, the receiver can automatically measure "eye-width" at user-selectable BERs and extrapolate BER from data accumulated over much shorter elapsed times than normally required. The transmitter can also generate a gapped clock.

Characteristics

GENERATOR

Clock -
External clock input:

Frequency: DC to 200 MHz.

Amplitude: 0.5 to 5.0 V p-p.

Connector: BNC.

Termination select: 50 Ohm to -2 V, +3 V, AC or GND.

Input range: ECL, TTL, PECL compatible.

Threshold resolution: 10 mV step.

External clock reference input:

Frequency: 10 MHz, ±100 ppm maximum.

Amplitude: 0.5 to 2.0 V p-p, AC coupled.

Termination: 50 Ohm.

Connector: BNC.

Internal synthesized clock source:

Frequency: 1 Hz to 200 MHz.

Resolution: 1 Hz.

Accuracy: 10 ppm.

BURST clock:

Programmable gap: 16 Kbits maximum, 8-Bit resolution.

Pattern Generator -
PRBS: 2^N - 1, N = 31, 23, 15, 11, 10, 9, 7.
Programmable word: 256 Kbits maximum, 8-Bit resolution.
Mark density: PRBS 2¹⁰ 1 (1/8, 1/4, 1/2, 3/4, 7/8).
Mixed mode frame: 256 Kbits maximum, 8-Bit resolution.
Error injection:

Error: Single, Rate, External (TTL).

Field select: Overhead, payload or both.

Error rates: Error rate of 10^-n, n = 3, 4, 5, 6, 7.

Outputs -
Data and clock outputs:

Format: NRZ.

Configurations: Differential (True/Complement).

Source impedance: 50 Ohm.

Connector: BNC.

Amplitude: 0.5 V to 2.0 V, 10 mV step.

Offset, 50 Ohm to GND: -2.0 V to +1.8, 10 mV step (termination to 50 Ohm will increase the range for PECL).

Data delay range: ±1.0 ns, 20 ps resolution.

Rise/fall time: 300 ps typical, 500 ps maximum (20 to 80%).

Pattern sync output:

Signal level: 250 mV_p-p into 50 Ohm load.

Auxiliary -
Data inhibit input: ECL, 50 Ohm to -2 V, BNC.
Clock disable input: ECL, 50 Ohm to -2 V, BNC.

ANALYZER

Data and Clock -
Data and clock inputs:

Clock input: External or internal from generator.

Data polarity: True/invert selectable.

Input mode select: Single-ended or differential.

Termination select: 50 Ohm to -2 V, +3 V, AC or GND.

Input range: ECL, TTL, PECL compatible.
Threshold resolution: 10 mV step.

Threshold resolution: 10 mV step.

Synchronization -
Auto search: Clock and data threshold, clock and data timing skew, data pattern and polarity.

Measurements -
Frequency: 1 Hz to 200 MHz.
Bit errors: Window, Totalize, Timed Test, Simultaneous 1's, 0's and All Errors.
BER test field: Overhead, payload or both.
Propagation delay: Up to 128 Kbits.
Eye-width: Up to 32 ns.

Reference Data Patterns -
Identical to Pattern Generator but independent.
Startup delay: 0 to 64 Kbits programmable.

Auxiliary Signals (BNC Connectors) -
Error count inhibit input: ECL, 50 Ohm to -2 V.
Error detect output: RZ, TTL, 50 Ohm source.
Analyzer clock disable: ECL, 50 Ohm to -2 V.
Data delay output: ECL, 50 Ohm source.

Common Characteristics

Pattern -
Controls: Start/Stop, Pause/Resume or Single Step.
Save/Load:

Floppy disk: 3.5 in.

Internal storage: 2 Mbits.

Pattern Editor Software requires PC running Windows 3.1 or above.

Remote Interface -
GPIB: IEEE 488.2 compatible.
RS-232C: DB9 connector.
Parallel printer: DB25 connector.
Monitor: DB15, VGA Analog Output.